Multi-Core Memory Through Parallel Access to Memory Chip Bit Cells

By Desmond on January 23rd, 2008

Muti-core CPU? Check. Multi-core RAM? Check. Wait, what? Imagine this being part of your checklist as you customize your PC to your liking. Typically when you hear the term multi-core you immediately think CPU right? Well, think again.

Joseph Ashwood, an independent security analyst claims to have outlined a revolutionary technology to unleash the power of parallel access to bit cells on memory chips. This new technology is called the “Ashwood architecture” and uses an integrated smart controller next to the memory array of the chip. [1]

“This new technology enables parallel data storage and access on a single nonvolatile memory chip. The scalability created by this technology provides superior speed in accessing and storing data with higher storage capacity at a single chip level. With on-chip power management, the technology is truly enabling for applications that require on-chip high-speed data transfer for various high-capacity, nonvolatile memory devices,” said the Carnegie Mellon evaluation. [2]

Ashwood’s design allows memory to actually become faster as it gets bigger, due to the way data is organized across individual memory cells. Ashwood says the ratio is almost 1:1 — doubling size should result in a doubling of speed — but it’s all theory for now, as he’s only gotten as far as the software simulation stage. Once a manufacturer commits to the tech, however, Ashwood says chips could be coming off fabs in as little as three months, but it’ll be interesting to see who signs up first. [3]

Yes, it’s true that RAM memory has seen increases in size (GB) and frequency (MHz). But at the end of the day, it still utilizes the same old architecture. In comparison with DDR RAM, Ashwoodâ€™s architecture goes inside the chip and reorganizes how the bit cells are accessed, thus utilizing them more efficiently. Transfer rates for Ashwoodâ€™s architecture are faster as well. Currently DDR2 DRAM only transfers information up to 12GB per second, while Ashwoodâ€™s architecture can achieve transfer rates of 16GB per second when using flash memory. Even though Joseph Ashwoodâ€™s multi-core memory is theoretically still in its design stages, imagine the doorways multi-core memory could open up for parallel computing. The future is parallel!